PATMOS 2012 - 22nd Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS2012

PATMOS is a series of international workshops having been held in several places in Europe. It has over the years evolved into a well established and outstanding series of open European events on power and timing aspects of integrated circuit design. The increased interest, especially in low-power design, adds further momentum to the expansion of the workshop. Despite its growth, PATMOS can still be considered as an informal but very focused conference, featuring high-level scientific presentations together with open discussions and panel sessions in a free and easy environment.
Scope

The objective of the workshop is to provide a forum to discuss and investigate the emerging problems in the design methodologies and CAD-tools for the new generation of IC technologies. A major emphasis of the technical program is on speed and low-power aspects with particular regard to modeling, characterization, design, and architectures. The scope of the workshop includes, but is not limited to design and CAD aspects of:

Low power design: high performance low power systems, ultra low power systems, special architectures.

Modeling and synthesis: timing, power, low-voltage, interconnect, crosstalk.

Timing design: clocking, synchronization, asynchronous and self timed systems, adiabatic switching.

Optimization: low voltage low power logic families, logic parallelization, pipelining, fast low power arithmetic.

Physical design: module generation, library optimization and characterization, area estimation.

Physical test and characterization: low VT low voltage process, SOI, IDDQ, models and parameter extraction, experimental design for process control.

Design methods and CAD tools: for low voltage low power design, high speed circuits.

Trade-offs between devices, architectures and technologies, benchmark comparison.