WACy 2011 - Workshop on Accelerator-based Computing for the Masses

As we move into an energy-constrained era, current general-purpose multicore processors will find it increasingly hard to scale up to application requirements in an efficient manner. This workshop envisions a radically different future in which the multicore chip includes specialized accelerator cores that take care of the bulk of the computation. We are already headed in this direction; 4 out of the Top 5 fastest supercomputers are hybrid designs based on GP-GPUs. Mainstream multicore chips already include diverse accelerators such as GP-GPUs and Cryptographic units. Vendors promise to deliver plenty more accelerators if we can figure out what needs acceleration and how to harness these diverse types of cores. These heterogeneous manycore chips that integrate novel accelerator units with general-purpose processors promise high levels of performance and energy-efficiency. At this time, there is a critical need for research to enable widespread use of manycore accelerators and GPUs across a wide variety of mainstream applications and programming paradigms

This workshop seeks to bring together computer architects, software researchers, and application developers for a discussion on the potential and challenges for the accelerator vision. We would like to understand the architecture and design of these manycore chips and how they integrate into the existing software stack. We would also like to understand the types of applications and the programming constructs that will help us harness their compute capabilities. We hope to develop a well-integrated program that addresses includes presentations on the systems architecture, software runtime, OS support, and applications for accelerators.

WACy'11 will be co-located with ICS 2011 in Tucson, Arizona. The workshop program will include presentations of peer-reviewed papers as well as a keynote.

The organizing committee is soliciting presentations on any topic related to compute accelerators, including

Novel accelerator and GP-GPU architectures.
How do we integrate GPUs, accelerators and CPUs for general purpose computing?
Memory system and Interconnects for GPUs and accelerators.
Accelerator-awareness in the general-purpose processor?
Runtime systems and programming environments for hybrid architectures
OS resource management and scheduling
Characterizing energy efficiency of accelerator-based computing
Profiling infrastructure to identify acceleratable parts of the application