DRSN 2019 - 9th International Workshop on High Performance and Dynamic Reconfigurable Systems and Networks (DRSN 2019)

Reconfigurable Systems (RS) and Networks on Chips (NoC) are increasingly finding use in applications that require high-performance computing (HPC), power-efficiency, or both. Field-Programmable Gate Arrays (FPGAs) are seeing adoption in mainstream for both big-data and big-compute applications. The use of NoCs - as opposed to conventional bus-based communication architectures - is already established in a variety of architectures.
While there is considerable maturity in the area of NoC and RS architectures, there is that familiar gap between the capability of such architectures, and the capability of programmers, compilers, and runtime systems to efficiently exploit the performance and efficiency dividends these architectures promise.
More specifically, the challenges -- and the corresponding opportunity for innovation -- can be broken down into four broad categories: programming, compilers, run-time infrastructures, and the architectures themselves. Wider adoption, especially of reconfigurable systems, is contingent on a synergetic development and maturity across these areas. Lack of such a synergy has been a major hurdle to RS and specifically FPGAs becoming more mainstream, but there are very strong indicators in the academia and the industry that this is changing. High Performance Reconfigurable Computing (HPRC) is specially getting widespread interest.
The International Workshop on High Performance and Dynamic Reconfigurable Systems and Networks (DRSN 2019) is intended to serve as a forum and bring together researchers and engineers in both academia and industry to exchange ideas, share experiences, and report original works about all aspects of reconfigurable systems and NoCs in high-performance and/or power-efficient systems. The challenges to wider adoption of these technologies, arising out of programming environments, compilers, and runtime systems are of special interest to this workshop, along with innovations at the architectural level.
The DRNS Workshop topics of interest include (but are not limited to) the following:
Heterogeneous High Performance Computing (HHPC) and High performance Reconfigurable Computing (HPRC) Applications
HPC applications on multi/many-core CPUs, GPUs and FPGAs
HHPC and HPRC for Scientific Applications
HHPC and HPRC for Machine Learning and Artificial Intelligence
HHPC and HPRC for Big-Data Applications
FPGAs for Edge Computing and Bump-in-the-Wire
Tools, Languages, Frameworks, Benchmarks, and DSE
Compilation, Programming Languages, and Domain-Specific Languages for HHPC and HPRC
Tools, Frameworks, Design-flows for HHPC and HPRC
Virtual Machines, Middleware, Run-time and Operating Systems for HHPC and HPRC
Domain Specific Languages (DSLs) for HHPC and HPRC
High-level and Pure Software Programming for Reconfigurable Computing Devices
Design Space Exploration (DSE) of Reconfigurable and/or NoC-based systems
Self-reconfiguration and self-optimization for HPC
Benchmarks and Evaluations
Benchmarks: Compute performance and/or power and cost efficiency for cloud/HPC with reconfigurable architectures using FPGAs
Area, energy, and performance evaluation
Comparative analysis of heterogeneous devices and frameworks for HPC
Networks and NoCs
Novel NoC Architectures for high-performance systems
Systems software support for advanced NoC-based systems
NoC-aware compilation and runtime systems
Mapping and scheduling for NoC-based systems
Case studies and FPGA-based implementation of reconfigurable systems and NoC-based systems
Others
Reliability, scalability, availability, and fault tolerance
Reconfigurable computing education