DRMC 2018 - 8th International Workshop on Dependable and Resilient Many-Core Computing (DRMC 2018)

Computing systems with a large number of processing units are increasingly common, both in the form of processors employing multiple execution cores (e.g., multi-core CPUs, GPUs, accelerators), or computing clusters with a large number of nodes. These many-core architectures bring up new capabilities, opportunities, as well as challenges. As the number of cores increases, so does the probability to have faults, both due to hardware issues (e.g., physical defects introduced during fabrication), software problems (e.g., a single crashed process bringing down the whole computation) or communication issues in the network infrastructure.
This workshop focuses on software and/or hardware solutions to dependability, resilience, and fault-tolerance in multi- and many-core systems.
The DRMC Workshop topics of interest include (but are not limited to) the following:
Dependable/Fault-Tolerant Many-Core Architectures
Power-Aware Many-Core Design
Dependable & Secure Many-Core Designs
Many-Core Development and Design Tools
Dependability and Fault Tolerance in Simulation
System-Level Many-Core Implementation
Many-Core Interconnect Technology
Many-Core System-On-Chip Development
Reconfigurable Computing and FPGAs
Design for Testing
Hardware and Software Debug Facilities
Many-Core Programming and Optimization for Dependability
Resilience of HPC and Many-Core Systems
Application Partitioning and Load Balancing
Hypervisors and Virtual Machine Technology
Trusted and Untrusted Environments
Virtualization for Dependability
Dependability through Multi-Threading / Multi-Processing
Fault Detection Techniques
Fault-Tolerant Software Design
Fault-Tolerant Hardware Design
Fault-Tolerant HW/SW Co-Design
Modeling and Simulation of Dependable and Fault Tolerant Systems
Formal Techniques for Dependable Hardware/Software Design