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TAU 2013 - 20th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU'13)

Date2013-03-24 - 2013-03-27

Deadline2012-10-01

VenueLake Tahoe, USA - United States USA - United States

Keywords

Websitehttp://www.tauworkshop.com/

Topics/Call fo Papers

The TAU series of workshops provide an informal forum for practitioners and researchers working on temporal aspects of integrated circuits to disseminate early work and engage in a free discussion of ideas.
TAU 2013 workshop invites submissions from all areas related to the timing properties of both digital and analog electronic systems, including but not limited to:
Transistor level models
Analog circuit modeling
Timing interfaces with mixed signal circuits
Reliability modeling and simulation
Circuit-level simulation of digital circuits
Simulation and characterization of SRAM circuits
Digital cell characterization for many corner/statistical timing
Timing-driven system design, synthesis and physical design
Sensitivity analysis
Full custom design analysis
Integrated functional-temporal analysis
Timing issues in low power design and testing
Power-delay trade-offs
Delay models and metrics
Layout impact on timing
Timing-driven layout optimization
Timing-driven synthesis and re-synthesis
Circuit optimization
Uncertainty-based analysis
Incorporation of manufacture impacts to timing
Reliability impact on performance
Process & environmental variation models
Statistical analysis technique
Clocking, synchronization, and skew
Clock domains, static/dynamic logic
Novel clocking and no-clock (Asynchronous) schemes
Timing implications of emerging technologies

Last modified: 2012-09-03 14:50:00