RAPIDO 2013 - RAPIDO - Workshop on Rapid Simulation & Performance Evaluation: Methods and Tools

The focus of the RAPIDO’13 Workshop is on methods and tools for rapid simulation and performance evaluation in embedded and high performance systems design. Given continuous advances in chip technology, it is to be expected that future-generation processors will integrate numerous units on a single die, including multiple processor cores, multiple levels of (shared/private) caches or memories, and multiple dedicated accelerators, which will be glued together through a network on-chip (NoC).

The design space is huge though:
How many cores do we need?
Should we have a homogeneous or a heterogeneous design?
When dynamic reconfiguration must be performed?
How many caches/memories do we need?
How to choose the instruction set(s) for these cores?
What are the best code optimizations for a given application?
How to combine the different metrics (e.g. energy, latency and throughput) into a global search space?
All these design questions lead to a huge design space that needs to be explored and which poses a grand challenge to search this space and to deliver an optimal design within the tight time-to-market budget.